DC-DC switching regulators, or, converters, are circuits that use an inductor, a transformer, or a capacitor as an energy storage element to allow the transfer of energy from a switched element connected to its input to its output in discrete packets during the charge phase of a cycle. One type of DC-DC switching regulator uses an inductor as the energy storage element and a capacitor as a charge storage element at the output. Feedback circuitry regulates the energy transfer from the switched element to the energy storage element so as to maintain a relatively constant voltage across the charge storage element, within the load limits of the circuit.
DC-DC switching regulators can be configured to step up (boost) or step down (buck) the output voltage, or both, and can be configured to invert output voltage with respect to input voltage. A benefit of DC-DC switching regulators is their relatively high efficiency. In basic configurations, a so-called “freewheeling” diode, such as a Schottky-type diode, is typically used to allow current to flow from the energy storage element to the charge storage element during the discharge phase of a cycle when the switching element is turned off, but which is reverse-biased during the charge phase of a cycle when the switching element is turned on. A typical operating frequency is on the order of 500 KHz, although the frequency is quite variable, depending on design considerations.
When DC-DC switching regulators are used in high current applications, however, the power dissipation induced by the freewheeling diode of basic designs can be excessive. To alleviate this problem, a switch is sometimes used in the place of the freewheeling diode, and the resulting regulator is said to be synchronous. The switch is typically a metal oxide semiconductor field effect (MOSFET) device.
FIG. 1 shows an exemplary prior art synchronous DC-DC buck regulator. The energy storage element is an inductor L, and the charge storage element is a capacitor C connected between the output and ground. The primary switch for the inductor is an n-type metal oxide semiconductor (NMOS) transistor T1, which is driven by a high side drive, HS Drive, at its control element, i.e., gate, to provide energy to inductor L from the power supply, VSUPPLY, when HS Drive is driven high. A second NMOS transistor T2 is connected between the common node of transistor T1 and inductor L, and ground, with its gate being driven by low side drive, LS Drive. As is known, LS Drive is the inverse of HS Drive, with a “dead zone” at transitions to prevent brief moments when both transistors would otherwise be on at the same time. Note that a parasitic diode DP exists in transistor T2, which must be oriented as shown, to ensure that it is not forward biased during the charge phase. Since parasitic diode DP has more impedance than transistor T2 during the discharge phase, it essentially serves no purpose in the circuit. In prior art configurations using a freewheeling diode, the diode would be placed where transistor T2 is in this circuit.
In operation, driving pulses are provided at the HS Drive input to the circuit, thereby turning transistor T1 on during those driving pulses. The time when transistor T1 is on is the charge phase of the buck regulator of FIG. 1. During the charge phase, current is driven through inductor L, charging up capacitor C to provide an output voltage VOUT. Transistor T2 is off, since LS Drive is low. As capacitor C charges up, the flow of current through inductor L builds its field.
When HS Drive goes low, transistor T1 turns off. The time when transistor T1 is off is the discharge phase. Transistor T2 is on, since LS Drive is high. As soon as transistor T1 is turned off, the voltage across inductor L reverses immediately to maintain current flow. As the inductor L field slowly collapses, current flows in a circuit through inductor L, capacitor C and transistor T2, thereby substantially maintaining the output voltage VOUT. The low impedance offered by transistor T2 provides reduced power dissipation, and therefore higher efficiency for the operation of the buck regulator circuit, as compared with prior art configurations that use a freewheeling diode.
The circuit in FIG. 1 includes a prior art overcurrent indicator circuit. The overcurrent indicator circuit is implemented by a third NMOS transistor T3 having its gate connected to the gate of transistor T1, its drain connected to VSUPPLY and its source connected to a senseFET input of an overcurrent sense circuit 10. The source of transistor T1 is connected to the L1 input of overcurrent sense circuit 10.
The transistor T3 is very small compared to transistor T1, for example having a size of approximately 1/10,000 the size of transistor T1, and so draws very little current, while providing a current that mirrors the current through transistor T1 to the senseFET input of overcurrent sense circuit 10, although scaled by the ratio of the size of transistor T1 to transistor T3, thus providing a scaled sense current to the overcurrent sense circuit 10. The voltage at the L1 input is provided as a reference for the sense operation. When the scaled sense current becomes larger than a predetermined amount corresponding to a peak current through transistor T1 that would overload the buck regulator circuit, an overcurrent signal can be provided as an output of the overcurrent sense circuit 10 so that, for example, other circuitry (not shown) can disable the HS Drive and prevent possible damage to the switching circuit.
Now, as mentioned above, the low impedance offered by transistor T2 provides reduced power dissipation, and therefore higher efficiency for the operation of the buck regulator circuit. This can be very important at high load currents. However, the presence of transistor T2 during low load current conditions in systems having a large output voltage dynamic range can be a disadvantage, for two reasons. First, in order to provide a large dynamic range for the output voltage, T2 will have to be much larger than would otherwise be necessary for the very low end of the output voltage range, and so its gate capacitance will be significantly higher than would otherwise be the case. As a result of this large gate capacitance, more energy could be required to switch the device on and off than would be lost through the freewheeling diode that transistor T2 replaces. Secondly, when the output current goes below a certain value, current will actually reverse through the inductor and flow from the output to ground during the second half of the cycle when T2 is on. This current is wasted via heat dissipation of the switching elements as well as discharge to ground.
The same problem arises in other synchronous DC-DC regulator circuits as well, for essentially the same reasons. For example, FIG. 2 shows an exemplary prior art synchronous buck-boost regulator. Like referenced elements operate as described above in connection with the regulator of FIG. 1. However, two additional switches can be seen, NMOS device T4 and pass gate transistor T5. Pass gate transistor T5 may be either an NMOS or PMOS transistor.
In operation, during the charge phase, when HS Drive is driven high, transistors T1 and T4 are turned on, while transistors T2 and T5 are turned off. Thus, current is driven through inductor L to ground, causing the field of inductor L to build. During the discharge phase, when LS Drive is driven high, transistors T2 and T5 are turned on, while transistors T1 and T4 are turned off. Thus, the voltage across inductor L reverses immediately to maintain current flow, and as the inductor L field slowly collapses, current flows in a circuit through inductor L, transistor T5, capacitor C and transistor T2, thereby charging capacitor C and building, and thereafter substantially maintaining, the output voltage VOUT, which can be driven to a higher voltage than the input voltage, which is VSUPPLY, since the voltage driving the charging of capacitor C is not tied to VSUPPLY, as it is in the circuit of FIG. 1. However, it can be seen that the same problems described above exist in the circuit of FIG. 2, as well.
U.S. Pat. No. 5,481,178 discloses a synchronous DC-DC regulator of the type in which current through the inductor is monitored by circuitry coupled to the inductor, and when the inductor current rises above a set threshold, the high side drive is turned off and the low side drive is turned on, for a set interval. Their arrangement forces the output voltage to an overvoltage condition, i.e., higher than normal, during low output current conditions, and then forces both the high side device and low side device off when an overvoltage condition is detected at the output, so that the output voltage is maintained by the charge on the capacitor during low output current conditions. In addition, they disclose an arrangement in which the current through the inductor is monitored by circuitry coupled to the inductor, and when the current through the inductor goes below another set threshold, it forces the low side device off in order to prevent the low side device from drawing power from the load during reversals in output inductor current.